Flash cells are used widely in the industry as memory storage. The Flash cell must be able to program, erase and retain charge on its floating gate. During program or erase the Flash cell is subject to high electric field to support oxide tunneling and hot electron injection. Those are the mechanisms that cause reliability failure.
Most of the available digital integrated circuits (IC) operate on rail-to-rail logic. Flash operation is distinctively analog. The digital information is stored in the analog distribution of the threshold voltage. In multi-level flash cells, multiple bits are stored by precise placement of threshold voltage in each cell. The readout of the threshold voltage requires precise placement of the sense amplifier decision threshold.
The voltage programming and readout are statistical, and there is therefore a probability of error in each decision. The use of error correction codes (ECC) enables reduction of the error rate to an acceptable value, e.g. 10−15.
There are currently three common methods of programming Flash memory: channel electron ejection, Fowler-Nordhiem (F-N) tunneling from the source or drain, and F-N tunneling from the channel. There are also three common methods for erasing data from the Flash memory: F-N tunneling through the channel, F-N tunneling through the source or drain, and F-N tunneling to the floating gate. These techniques, however, require a high electric field in the oxide and may create traps and leakage current.
The result of fixed program and erase (P/E) cycles with fixed voltage may be significant loss of threshold voltage margin between the program level and the erase level, due to the fact that the programming window remains fixed. Currently known flash devices may use feedback P/E mechanisms, and may employ program and verify or erase and verify. During the verify stage, current methods may measure the correct voltage margin and stop the operation when it is achieved. The result may be a significant increase of cycle count for a given margin.
A second effect of the P/E cycles is the increase of the threshold variance. As the number of cycles increases, the number of traps also increases. The average number of traps reduces the threshold window as discussed above. However, it also increases the threshold variance for every level in the program. The relation to the number of cycles is derived in the empirical model described in: Mielke, N. Belgal, H. Kalastirsky, I. Kalavade, P. Kurtz, A. Meng, Q. Righos, N. Wu, J. “Flash EEPROM Threshold Instabilities Due to Charge Trapping During Program/Erase Cycling”, IEEE Transactions on Device and Materials Reliability, Vol. 4, No. 3, September 2004, p 335-344, which is incorporated herein in its entirety by reference.
The bit error rate of a given Flash memory may be related to the threshold voltage window and to the threshold voltage variance at the highest cycle count. The number of errors may be calculated based on Gaussian distribution of the threshold voltage:
      P    bit    =            erfc      ⁡              (                              W            σ                                              (                                                N                  Levels                                -                1                            )                        ⁢            2            ⁢                          2                                      )              ×                            N          Levels                -        2                              N          Levels                ·                              log            2                    ⁡                      (                          N              Levels                        )                              Where:                σ≡maximum threshold variance        W≡minimum threshold window        N≡Number of levels (2, 4, 8)        
The minimum threshold voltage window and the maximum threshold voltage variance may be measured at the maximum cycle counts of a given device (100,000 at Single Level Cell, 10,000 at Multi-Level Cell and 1,000 at 3 bits per cell). The device bit error rate (BER) may therefore not be constant with respect to the cycle count and the numbers of errors may constantly increase as the number of cycle increases. The Flash memory controller ECC is designed to correct the highest number of errors at the maximum number of cycles.
It would therefore be advantageous to have a flash memory device with a constant bit error rate, independently of the number of P/E cycles.